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d a t a sh eet preliminary speci?cation supersedes data of 2002 may 22 2002 nov 22 integrated circuits uda1352ts 48 khz iec 60958 audio dac
2002 nov 22 2 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352ts contents 1 features 1.1 general 1.2 control 1.3 iec 60958 input 1.4 digital sound processing and dac 2 applications 3 general description 4 ordering information 5 quick reference data 6 block diagram 7 pinning 8 functional description 8.1 clock regeneration and lock detection 8.2 mute 8.3 auto mute 8.4 data path 8.5 control 9 l3-bus description 9.1 general 9.2 device addressing 9.3 register addressing 9.4 data write mode 9.5 data read mode 9.6 initialization string 10 i 2 c-bus description 10.1 characteristics of the i 2 c-bus 10.2 bit transfer 10.3 byte transfer 10.4 data transfer 10.5 start and stop conditions 10.6 acknowledgment 10.7 device address 10.8 register address 10.9 write and read data 10.10 write cycle 10.11 read cycle 11 spdif signal format 11.1 spdif channel encoding 11.2 spdif hierarchical layers for audio data 11.3 spdif hierarchical layers for digital data 11.4 timing characteristics 12 register mapping 12.1 spdif mute setting (write) 12.2 power-down settings (write) 12.3 volume control left and right (write) 12.4 sound feature mode, treble and bass boost settings (write) 12.5 mute (write) 12.6 polarity (write) 12.7 spdif input settings (write) 12.8 interpolator status (read-out) 12.9 spdif status (read-out) 12.10 channel status (read-out) 12.11 fpll status (read-out) 13 limiting values 14 thermal characteristics 15 characteristics 16 timing characteristics 17 application information 18 package outline 19 soldering 19.1 introduction to soldering surface mount packages 19.2 reflow soldering 19.3 wave soldering 19.4 manual soldering 19.5 suitability of surface mount ic packages for wave and reflow soldering methods 20 data sheet status 21 definitions 22 disclaimers 23 purchase of philips i 2 c components
2002 nov 22 3 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352ts 1 features 1.1 general 2.7 to 3.6 v power supply integrated digital filter and digital-to-analog converter (dac) 256f s system clock output 20-bit data path in interpolator high performance no analog post filtering required for dac supporting sampling frequencies from 28 up to 55 khz. 1.2 control controlled either by means of static pins, i 2 c-bus or l3-bus microcontroller interface. 1.3 iec 60958 input on-chip amplifier for converting iec 60958 input to cmos levels lock indication signal available on pin lock information of the pulse code modulation (pcm) status bit and the non-pcm data detection is available on pin pcmdet for left and right 40 key channel-status bits available via l3-bus or i 2 c-bus interface. 1.4 digital sound processing and dac automatic de-emphasis when using iec 60958 input with 32.0, 44.1 and 48.0 khz audio sample frequencies soft mute by means of a cosine roll-off circuit selectable via pin mute, l3-bus or i 2 c-bus interface left and right independent db linear volume control with 0.25 db steps from 0 to - 50 db, 1 db steps to - 60, - 66 and - db bass boost and treble control in l3-bus or i 2 c-bus mode interpolating filter (f s to 64f s ) by means of a cascade of a recursive filter and a fir filter fifth-order noise shaper (operating at 64f s ) generates the bitstream for the dac filter stream dac (fsdac). 2 applications digital audio systems. 3 general description the uda1352ts is a single-chip iec 60958 audio decoder with an integrated stereo dac employing bitstream conversion techniques. a lock indication signal is available on pin lock, indicating that the iec 60958 decoder is locked. a separate pin pcmdet is available to indicate whether or not the pcm data is applied to the input. by default, the dac output is muted when the decoder is out-of-lock. however, this setting can be overruled in the l3-bus or i 2 c-bus mode. the uda1352ts has iec 60958 input to the dac only and is in ssop28 package. besides the uda1352ts, the uda1352hl is also available. the uda1352hl is the full featured version in lqfp48 package. 4 ordering information type number package name description version uda1352ts ssop28 plastic shrink small outline package; 28 leads; body width 5.3 mm sot341-1
2002 nov 22 4 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352ts 5 quick reference data v ddd =v dda = 3.0 v; iec 60958 input with f s = 48.0 khz; t amb =25 c; r l =5k w ; all voltages measured with respect to ground; unless otherwise speci?ed. note 1. the output voltage of the dac is proportional to the dac power supply voltage. symbol parameter conditions min. typ. max. unit supplies v ddd digital supply voltage 2.7 3.0 3.6 v v dda analog supply voltage 2.7 3.0 3.6 v i dda(dac) analog supply current of dac power-on - 3.3 - ma power-down; clock off - 35 -m a i dda(pll) analog supply current of pll - 0.3 - ma i ddd(c) digital supply current of core - 9 - ma i ddd digital supply current - 0.3 - ma p power dissipation dac in playback mode - 38 - mw dac in power-down mode - tbf - mw general t rst reset active time - 250 -m s t amb ambient temperature - 40 - +85 c digital-to-analog converter v o(rms) output voltage (rms value) f i = 1.0 khz tone at 0 dbfs; note 1 850 900 950 mv d v o unbalance of output voltages f i = 1.0 khz tone - 0.1 0.4 db (thd+n)/s total harmonic distortion-plus-noise to signal ratio f i = 1.0 khz tone at 0 dbfs -- 82 - 77 db at - 40 dbfs; a-weighted -- 60 - 52 db s/n signal-to-noise ratio f i = 1.0 khz tone; code = 0; a-weighted 95 100 - db a cs channel separation f i = 1.0 khz tone - 110 - db
2002 nov 22 5 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352ts 6 block diagram handbook, full pagewidth mgu655 voutr 5 17 reset clock and timing circuit pcmdet 1 lock 16 n.c. 21, 22, 27 dac voutl 15 dac v dda(dac) 14 v ssa(dac) 20 v ref 19 test1 2 test2 18 audio feature processor interpolator noise shaper iec 60958 decoder slicer l3-bus or i 2 c-bus interface non-pcm data sync detector 8 l3data 9 l3clock 10 l3mode 25 da1 28 da0 3 v ddd 7 v ssd 6 v ddd(c) 12 v ssd(c) 24 v dda(pll) 23 v ssa(pll) 13 spdif 26 4 selstatic seliic 11 mute uda1352ts fig.1 block diagram.
2002 nov 22 6 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352ts 7 pinning note 1. see table 1. symbol pin type (1) description pcmdet 1 do pcm detection indicator output test1 2 do test pin 1; must be left open-circuit in application v ddd 3 ds digital supply voltage seliic 4 did i 2 c-bus or l3-bus mode selection input reset 5 did reset input v ddd(c) 6 ds digital supply voltage for core v ssd 7 dgnd digital ground l3data 8 iic l3-bus or i 2 c-bus interface data input and output l3clock 9 dis l3-bus or i 2 c-bus interface clock input l3mode 10 dis l3 interface mode input mute 11 did mute control input v ssd(c) 12 dgnd digital ground for core spdif 13 aio iec 60958 channel input v dda(dac) 14 as analog supply voltage for dac voutl 15 aio dac left channel analog output lock 16 do spdif and pll lock indicator output voutr 17 aio dac right channel analog output test2 18 did test pin 2; must be connected to digital ground (v ssd ) in application v ref 19 aio dac reference voltage v ssa(dac) 20 agnd analog ground for dac n.c. 21 - not connected n.c. 22 - not connected v ssa(pll) 23 agnd analog ground for pll v dda(pll) 24 as analog supply voltage for pll da1 25 disu a1 device address selection input selstatic 26 diu static pin control selection input n.c. 27 - not connected (reserved) da0 28 did a0 device address selection input
2002 nov 22 7 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352ts table 1 pin types type description ds digital supply dgnd digital ground as analog supply agnd analog ground di digital input dis digital schmitt-triggered input did digital input with internal pull-down resistor disd digital schmitt-triggered input with internal pull-down resistor diu digital input with internal pull-up resistor disu digital schmitt-triggered input with internal pull-up resistor do digital output dio digital input and output dios digital schmitt-triggered input and output iic input and open-drain output for i 2 c-bus aio analog input and output handbook, halfpage uda1352ts mgu654 1 2 3 4 5 6 7 8 9 10 11 12 13 14 pcmdet test1 v ddd seliic reset v ddd(c) v ssd l3data l3clock l3mode mute v ssd(c) spdif v dda(dac) da0 n.c. selstatic da1 v dda(pll) v ssa(pll) n.c. n.c. v ssa(dac) v ref test2 voutr lock voutl 28 27 26 25 24 23 22 21 20 19 18 17 16 15 fig.2 pin configuration.
2002 nov 22 8 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352ts 8 functional description 8.1 clock regeneration and lock detection the uda1352ts contains an on-board pll for regenerating a system clock from the iec 60958 input bitstream. remark: if there is no input signal, the pll generates a minimum frequency and the output spectrum shifts accordingly. since the analog output does not have an analog mute, this means noise that is out of band under normal conditions can move into the audio band. when the on-board clock locks to the incoming frequency, the lock indicator bit is set and can be read via the l3-bus or i 2 c-bus interface. internally, the pll lock indication can be combined with the pcm status bit of the input data stream and the status whether any burst preamble is detected or not. by default, when both the iec 60958 decoder and the on-board clock have locked to the incoming signal and the input data stream is pcm data, pin lock will be asserted. however, when the ic is locked but the pcm status bit reports non-pcm data, pin lock is returned to low level. this combination of the lock status and the pcm detection can be overruled by the l3-bus or i 2 c-bus register setting. the lock indication output can be used, for example, for muting purposes. the lock signal can be used to drive an external analog muting circuit to prevent out of band noise from becoming audible when the pll runs at its minimum frequency (e.g. when there is no spdif input signal). the uda1352ts has a dedicated pin pcmdet to indicate whether valid pcm data stream is detected or (supposed to be) non-pcm data is detected. 8.2 mute the uda1352ts is equipped with a cosine roll-off mute in the dsp data path of the dac part. muting the dac (by pin mute or via bit mt in the l3-bus or i 2 c-bus mode) will result in a soft mute as shown in fig.3. the cosine roll-off soft mute takes 32 32 samples = 23 ms at 44.1 khz sampling frequency. when operating in the l3-bus or i 2 c-bus mode, the device will mute on start-up. in the l3-bus or i 2 c-bus mode, it is necessary to explicitly switch off the mute for audio output by means of bit mt in the device register. in the l3-bus or i 2 c-bus mode, pin mute will at all time mute the output signal. this is in contrast to the uda1350 and the uda1351 in which pin mute in the l3-bus mode does not have any function. 8.3 auto mute by default, the dac outputs will be muted until the uda1352ts is locked, regardless of the level on pin mute or the state of bit mt. in this way, only valid data will be passed to the outputs. this mute is done in the spdif interface and is a hard mute, not a cosine roll-off mute. if needed, this muting can be bypassed by setting bit mutebp = 1 via the l3-bus or i 2 c-bus interface. as a result, the uda1352ts will no longer mute during out-of-lock situations. handbook, halfpage 010 51525 1 0 0.8 mgu119 20 0.6 0.4 0.2 t (ms) mute factor fig.3 mute as a function of raised cosine roll-off.
2002 nov 22 9 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352ts 8.4 data path the uda1352ts data path consists of the iec 60958 decoder, the audio feature processor, the digital interpolator and noise shaper and the dacs. 8.4.1 iec 60958 input the iec 60958 decoder features an on-chip amplifier with hysteresis, which amplifies the spdif input signal to cmos level (see fig.4). all 24 bits of data for left and right are extracted from the input bitstream as well as 40 channel status bits for left and right. these bits can be read via the l3-bus or i 2 c-bus interface. the uda1352ts supports the following sample frequencies and data bit rates: f s = 32.0 khz, resulting in a data rate of 2.048 mbits/s f s = 44.1 khz, resulting in a data rate of 2.8224 mbits/s f s = 48.0 khz, resulting in a data rate of 3.072 mbits/s. the uda1352ts supports timing levels i, ii and iii, as specified by the iec 60958 standard. this means that the accuracy of the above mentioned sampling frequencies depends on the timing level i, ii or iii as mentioned in section 11.4.1. 8.4.2 a udio feature processor the audio feature processor automatically provides de-emphasis for the iec 60958 data stream in the static pin control mode and default mute at start-up in the l3-bus or i 2 c-bus mode. when used in the l3-bus or i 2 c-bus mode, it provides the following additional features: left and right independent volume control bass boost control treble control mode selection of the sound processing bass boost and treble filters: flat, minimum and maximum soft mute control with raised cosine roll-off. 8.4.3 i nterpolator the uda1352ts includes an on-board interpolating filter which converts the incoming data stream from 1f s to 64f s by cascading a recursive filter and a fir filter. table 2 interpolator characteristics 8.4.4 n oise shaper the fifth-order noise shaper operates at 64f s . it shifts in-band quantization noise to frequencies well above the audio band. this noise shaping technique enables high signal-to-noise ratios to be achieved. the noise shaper output is converted to an analog signal using a filter stream dac. handbook, halfpage mgu656 13 spdif 75 w 180 pf 10 nf uda1352ts fig.4 iec 60958 input circuit and typical application. parameter conditions value (db) pass-band ripple 0 to 0.45f s 0.03 stop band >0.55f s - 50 dynamic range 0 to 0.45f s 114 dc gain -- 5.67
2002 nov 22 10 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352ts 8.4.5 f ilter stream dac the filter stream dac (fsdac) is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. the filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. in this way, very high signal-to-noise performance and low clock jitter sensitivity is achieved. a post filter is not needed due to the inherent filter function of the dac. on-board amplifiers convert the fsdac output current to an output voltage signal capable of driving a line output. the output voltage of the fsdac is scaled proportionally with the power supply voltage. 8.5 control the uda1352ts can be controlled by means of static pins (when pin selstatic = high), via the i 2 c-bus (when pin selstatic = low and pin seliic = high) or via the l3-bus (when pins selstatic and seliic are low). for optimum use of the features of the uda1352ts, the l3-bus or i 2 c-bus mode is recommended since only basic functions are available in the static pin control mode. it should be noted that the static pin control mode and the l3-bus or i 2 c-bus mode are mutually exclusive. 8.5.1 s tatic pin control mode the default values for all non-pin controlled settings are identical to the default values at start-up in the l3-bus or i 2 c-bus mode (see table 3). table 3 pin description of static pin control mode pin name value function mode selection pin 26 selstatic 1 select static pin control mode; must be connected to v ddd input pins 5 reset 0 normal operation 1 reset 9 l3clock 0 must be connected to v ssd 10 l3mode 0 must be connected to v ssd 8 l3data 0 must be connected to v ssd 11 mute 0 no mute 1 mute active status pins 1 pcmdet 0 non-pcm data or burst preamble detected 1 pcm data detected 16 lock 0 clock regeneration and iec 60958 decoder out-of-lock or non-pcm data detected 1 clock regeneration and iec 60958 decoder locked and pcm data detected test pins 2 test1 - must be left open-circuit 18 test2 0 must be connected to v ssd
2002 nov 22 11 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352ts 8.5.2 l3- bus or i 2 c- bus mode the l3-bus or i 2 c-bus mode allows maximum flexibility in controlling the uda1352ts (see table 4). it should be noted that in the l3-bus or i 2 c-bus mode, several base-line functions are still controlled by pins on the device and that, on start-up in the l3-bus or i 2 c-bus mode, the output is explicitly muted by bit mt via the l3-bus or i 2 c-bus interface. table 4 pin description in the l3-bus or i 2 c-bus mode pin name value function mode selection pins 26 selstatic 0 select l3-bus mode or i 2 c-bus mode; must be connected to v ssd 4 seliic 0 select l3-bus mode; must be connected to v ssd 1 select i 2 c-bus mode; must be connected to v ddd input pins 5 reset 0 normal operation 1 reset 8 l3data - must be connected to the l3-bus - must be connected to the sda line of the i 2 c-bus 9 l3clock - must be connected to the l3-bus - must be connected to the scl line of the i 2 c-bus 10 l3mode - must be connected to the l3-bus 11 mute 0 no mute 1 mute active status pins 1 pcmdet 0 non-pcm data or burst preamble detected 1 pcm data detected 16 lock 0 clock regeneration and iec 60958 decoder out-of-lock or non-pcm data detected 1 clock regeneration and iec 60958 decoder locked and pcm data detected test pins 2 test1 - must be left open-circuit 18 test2 0 must be connected to v ssd
2002 nov 22 12 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352ts 9 l3-bus description 9.1 general the uda1352ts has an l3-bus microcontroller interface and all the digital sound processing features and various system settings can be controlled by a microcontroller. the controllable settings are: restoring l3-bus default values power-on selection of filter mode and settings of treble and bass boost volume settings left and right selection of soft mute via cosine roll-off and bypass of auto mute. the readable settings are: mute status of interpolator pll locked spdif input signal locked audio sample frequency valid pcm data detected pre-emphasis of the iec 60958 input signal accuracy of the clock. the exchange of data and control information between the microcontroller and the uda1352ts is lsb first and is accomplished through the serial hardware l3-bus interface comprising the following pins: l3data: data line l3mode: mode line l3clock: clock line. the l3-bus format has two modes of operation: address mode data transfer mode. the address mode is used to select a device for a subsequent data transfer. the address mode is characterized by l3mode being low and a burst of 8 pulses on l3clock, accompanied by 8 bits (see fig.5). the data transfer mode is characterized by l3mode being high and is used to transfer one or more bytes representing a register address, instruction or data. basically, two types of data transfers can be defined: write action: data transfer to the device read action: data transfer from the device. remark: when the device is powered-up, at least one l3clock pulse must be given to the l3-bus interface to wake-up the interface before starting sending to the device (see fig.5). this is only needed once after the device is powered-up. 9.2 device addressing the device address consists of 1 byte with: data operating mode (dom) bits 0 and 1 representing the type of data transfer (see table 5) address bits 2 to 7 representing a 6-bit device address. the bits 2 and 3 of the address can be selected via the external pins da0 and da1, which allows up to 4 uda1352ts devices to be independently controlled in a single application. the primary address of the uda1352ts is 001000 (lsb to msb) and the default address is 011000. table 5 selection of data transfer 9.3 register addressing after sending the device address (including dom bits), indicating whether the information is to be read or written, one data byte is sent using bit 0 to indicate whether the information will be read or written and bits 1 to 7 for the destination register address. basically, there are three methods for register addressing: 1. addressing for write data: bit 0 is logic 0 indicating a write action to the destination register, followed by bits 1 to 7 indicating the register address (see fig.5) 2. addressing for prepare read: bit 0 is logic 1, indicating that data will be read from the register (see fig.6) 3. addressing for data read action. here, the device returns a register address prior to sending data from that register. when bit 0 is logic 0, the register address is valid; when bit 0 is logic 1, the register address is invalid. dom transfer bit 0 bit 1 0 0 not used 1 0 not used 0 1 write data or prepare read 1 1 read data
2002 nov 22 13 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352ts this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... mgs753 l3clock l3mode l3data 0 write l3 wake-up pulse after power-up device address dom bits register address data byte 1 data byte 2 10 fig.5 data write mode (for l3-bus version 2). mbl565 l3clock l3mode l3data 0 read valid/invalid device address prepare read send by the device dom bits register address device address register address data byte 1 data byte 2 111 0/1 1 fig.6 data read mode.
2002 nov 22 14 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352ts 9.4 data write mode the data write mode is explained in the signal diagram of fig.5. for writing data to a device, 4 bytes must be sent (see table 6): 1. one byte starting with 01 for signalling the write action to the device, followed by the device address (011000 for the uda1352ts default) 2. one byte starting with a 0 for signalling the write action, followed by 7 bits indicating the destination register address in binary format with a6 being the msb and a0 being the lsb 3. one data byte (from the two data bytes) with d15 being the msb 4. one data byte (from the two data bytes) with d0 being the lsb. it should be noted that each time a new destination register address needs to be written, the device address must be sent again. 9.5 data read mode to read data from the device, a prepare read must first be done and then data read. the data read mode is explained in the signal diagram of fig.6. for reading data from a device, the following 6 bytes are involved (see table 7): 1. one byte with the device address, including 01 for signalling the write action to the device 2. one byte is sent with the register address from which data needs to be read; this byte starts with a 1, which indicates that there will be a read action from the register, followed by seven bits for the source register address in binary format, with a6 being the msb and a0 being the lsb 3. one byte with the device address preceded by 11 is sent to the device; the 11 indicates that the device must write data to the microcontroller 4. one byte, sent by the device to the bus, with the (requested) register address and a flag bit indicating whether the requested register was valid (bit is logic 0) or invalid (bit is logic 1) 5. one byte (from the two bytes), sent by the device to the bus, with the data information in binary format, with d15 being the msb 6. one byte (from the two bytes), sent by the device to the bus, with the data information in binary format, with d0 being the lsb. table 6 l3-bus write data table 7 l3-bus read data byte l3-bus mode action first in time last in time bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 1 address device address 0 1 da0 da1 1000 2 data transfer register address 0 a6 a5 a4 a3 a2 a1 a0 3 data transfer data byte 1 d15 d14 d13 d12 d11 d10 d9 d8 4 data transfer data byte 2 d7 d6 d5 d4 d3 d2 d1 d0 byte l3-bus mode action first in time last in time bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 1 address device address 0 1 da0 da1 1000 2 data transfer register address 1 a6 a5 a4 a3 a2 a1 a0 3 address device address 1 1 da0 da1 1000 4 data transfer register address 0 or 1 a6 a5 a4 a3 a2 a1 a0 5 data transfer data byte 1 d15 d14 d13 d12 d11 d10 d9 d8 6 data transfer data byte 2 d7 d6 d5 d4 d3 d2 d1 d0
2002 nov 22 15 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352ts 9.6 initialization string for proper and reliable operation, the uda1352ts must be initialized in the l3-bus mode. this is required to have the pll start-up after powering up of the device under all conditions. the initialization string is given in table 8. table 8 l3-bus initialization string and set defaults after power-up byte l3-bus mode action first in time last in time bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 1 address init string device address 0 1 da0 da1 1 0 0 0 2 data transfer register address 0 1 0 0 0 0 0 0 3 data transfer data byte 1 0 0 0 0 0 0 0 0 4 data transfer data byte 2 0 0 0 0 0 0 0 1 5 address set defaults device address 0 1 da0 da1 1 0 0 0 6 data transfer register address 0 1 1 1 1 1 1 1 7 data transfer data byte 1 0 0 0 0 0 0 0 0 8 data transfer data byte 2 0 0 0 0 0 0 0 0 10 i 2 c-bus description 10.1 characteristics of the i 2 c-bus the bus is for 2-way, 2-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to the v dd via a pull-up resistor when connected to the output stages of a microcontroller. for a 400 khz ic the recommendation for this type of bus from philips semiconductors must be followed (e.g. up to loads of 200 pf on the bus a pull-up resistor can be used, between 200 to 400 pf a current source or switched resistor must be used). data transfer can only be initiated when the bus is not busy. 10.2 bit transfer one data bit is transferred during each clock pulse (see fig.7). the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as control signals. the maximum clock frequency is 400 khz. to be able to run on this high frequency all the inputs and outputs connected to this bus must be designed for this high-speed i 2 c-bus according to specification the i 2 c-bus and how to use it , (order code 9398 393 40011). handbook, full pagewidth mbc621 data line stable; data valid change of data allowed sda scl fig.7 bit transfer on the i 2 c-bus.
2002 nov 22 16 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352ts 10.3 byte transfer each byte (8 bits) is transferred with the msb first (see table 9). table 9 byte transfer 10.4 data transfer a device generating a message is a transmitter, a device receiving a message is the receiver. the device that controls the message is the master and the devices which are controlled by the master are the slaves. 10.5 start and stop conditions both data and clock line will remain high when the bus is not busy. a high-to-low transition of the data line, while the clock is high, is defined as a start condition (s); see fig.8. a low-to-high transition of the data line while the clock is high is defined as a stop condition (p). msb bit number lsb 76543210 handbook, full pagewidth mbc622 sda scl p stop condition sda scl s start condition fig.8 start and stop conditions on the i 2 c-bus. 10.6 acknowledgment the number of data bits transferred between the start and stop conditions from the transmitter to receiver is not limited. each byte of eight bits is followed by one acknowledge bit (see fig.9). at the acknowledge bit the data line is released by the master and the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed must generate an acknowledge after the reception of each byte. also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges has to pull-down the sda line during the acknowledge clock pulse, so that the sda line is stable low during the high period of the acknowledge related clock pulse. set-up and hold times must be taken into account. a master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this event, the transmitter must leave the data line high to enable the master to generate a stop condition.
2002 nov 22 17 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352ts handbook, full pagewidth mbc602 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver scl from master fig.9 acknowledge on the i 2 c-bus. 10.7 device address before any data is transmitted on the i 2 c-bus, the device which should respond is addressed first. the addressing is always done with byte 1 transmitted after the start procedure. the device address can be one out of four, being set by pin da0 and pin da1. the uda1352ts acts as a slave receiver or a slave transmitter. therefore, the clock signal scl is only an input signal. the data signal sda is a bidirectional line. the uda1352ts device address is shown in table 10. table 10 i 2 c-bus device address 10.8 register address the register addresses in the i 2 c-bus mode are the same as in the l3-bus mode. 10.9 write and read data the i 2 c-bus configuration for a write and read cycle are shown respectively in tables 11 and 12. the write cycle is used to write groups of two bytes to the internal registers for the digital sound feature control and system setting. it is also possible to read these locations for the device status information. device address r/ w a6 a5 a4 a3 a2 a1 a0 - 1 0 0 1 1 da1 da0 0/1
2002 nov 22 18 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352ts this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 10.10 write cycle the i 2 c-bus configuration for a write cycle is shown in table 11. the write cycle is used to write the data to the internal registers. the device and register addresses are one byte each, the setting data is always a pair of two bytes. the format of the write cycle is as follows: 1. the microcontroller starts with a start condition (s). 2. the first byte (8 bits) contains the device address 1001 110 and a logic 0 (write) for the r/ w bit. 3. this is followed by an acknowledge (a) from the uda1352ts. 4. after this the microcontroller writes the 8-bit register address (addr) where the writing of the register content of the uda1 352ts must start. 5. the uda1352ts acknowledges this register address (a). 6. the microcontroller sends 2 bytes data with the most significant (ms) byte first and then the least significant (ls) byte. aft er each byte an acknowledge is followed from the uda1352ts. 7. if repeated groups of 2 bytes are transmitted, then the register address is auto incremented. after each byte an acknowledge is followed from the uda1352ts. 8. finally, the uda1352ts frees the i 2 c-bus and the microcontroller can generate a stop condition (p). table 11 master transmitter writes to the uda1352ts registers in the i 2 c-bus mode. note 1. auto increment of register address. device address r/ w register address data 1 data 2 (1) data n (1) s 1001 110 0 a addr a ms1 a ls1 a ms2 a ls2 a msn a lsn a p acknowledge from uda1352ts
2002 nov 22 19 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352ts this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 10.11 read cycle the read cycle is used to read the data values from the internal registers. the i 2 c-bus configuration for a read cycle is shown in table 12. the format of the read cycle is as follows: 1. the microcontroller starts with a start condition (s). 2. the first byte (8 bits) contains the device address 1001 110 and a logic 0 (write) for the r/ w bit. 3. this is followed by an acknowledge (a) from the uda1352ts. 4. after this the microcontroller writes the register address (addr) where the reading of the register content of the uda1352ts must start. 5. the uda1352ts acknowledges this register address. 6. then the microcontroller generates a repeated start (sr). 7. then the microcontroller generates the device address 1001 110 again, but this time followed by a logic 1 (read) of the r/ w bit. an acknowledge is followed from the uda1352ts. 8. the uda1352ts sends 2 bytes data with the most significant (ms) byte first and then the least significant (ls) byte. after eac h byte an acknowledge is followed from the microcontroller. 9. if repeated groups of 2 bytes are transmitted, then the register address is auto incremented. after each byte an acknowledge is followed from the microcontroller. 10. the microcontroller stops this cycle by generating a negative acknowledge (na). 11. finally, the uda1352ts frees the i 2 c-bus and the microcontroller can generate a stop condition (p). table 12 master transmitter reads from the uda1352ts registers in the i 2 c-bus mode. note 1. auto increment of register address. device address r/ w register address device address r/ w data 1 data 2 (1) data n (1) s 1001 110 0 a addr a sr 1001 110 1 a ms1 a ls1 a ms2 a ls2 a msn a lsn na p acknowledge from uda1352ts acknowledge from master
2002 nov 22 20 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352ts 11 spdif signal format 11.1 spdif channel encoding the digital signal is coded using bi-phase mark code (bmc), which is a kind of phase-modulation. in this scheme, a logic 1 in the data corresponds to two zero-crossings in the coded signal, and a logic 0 to one zero-crossing. an example of the encoding is given in fig.10. 11.2 spdif hierarchical layers for audio data from an abstract point of view an spdif signal can be represented as in fig.11. a 2-channel pcm signal can be transmitted as various sequential blocks. each block in turn consists of 192 frames. each frame contains two sub-frames, one for each channel. each sub-frame is preceded by a preamble. there are three types of preambles being b, m and w. preambles can be spotted easily in an spdif stream because these sequences can never occur in the channel parts of a valid spdif stream. table 13 indicates the values of the preambles. a sub-frame in turn contains a single audio sample which may be up to 24 bits wide, a validity bit which indicates whether the sample is valid, a single bit of user data, and a single bit of channel status. finally, there is a parity bit for this particular sub-frame (see fig.12). the data bits from 4 to 31 in each sub-frame will be modulated using a bmc scheme. the sync preamble actually contains a violation of the bmc scheme and consequently can be detected easily. table 13 preambles 11.3 spdif hierarchical layers for digital data the difference with the audio format is that the data contained in the spdif signal is not audio but is digital data. when transmitting digital data via spdif using the iec 60958 protocol, the allocation of the bits inside the data word is done as shown in table 14. table 14 bit allocation for digital data as shown in table 14 and fig.13, the non-pcm encoded data bitstreams are transferred within the basic 16 bits data area of the iec 60958 sub-frames [time-slots 12 (lsb) to 27 (msb)]. handbook, halfpage data clock bmc mgu606 fig.10 bi-phase mark encoding. preceding state channel coding 01 b 1110 1000 0001 0111 m 1110 0010 0001 1101 w 1110 0100 0001 1011 field iec 60958 time slot bits description 0 to 3 preamble according to iec 60958 4 to 7 auxiliary bits not used; all logic 0 8 to 11 unused data bits not used; all logic 0 12 16 bits data sections of the digital bitstream 13 user data according to iec 60958 14 to 27 16 bits data sections of the digital bitstream 28 validity bit according to iec 60958 29 user data according to iec 60958 30 channel status bit according to iec 60958 31 parity bit according to iec 60958
2002 nov 22 21 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352ts handbook, full pagewidth channel 1 mmm ww w b channel 2 channel 1 sub-frame channel 2 channel 1 channel 2 channel 1 channel 2 frame 0 frame 191 frame 191 block mgu607 sub-frame fig.11 spdif block format. handbook, full pagewidth sync preamble auxiliary 03478 27 28 31 l s b l s b m s b p audio sample word c u v validity flag user data channel status parity bit mgu608 fig.12 sub-frame format in audio mode. handbook, full pagewidth sync preamble auxiliary 03478 27 28 31 l s b l s b 11 12 l s b m s b p 16-bit data stream unused data c u v validity flag user data channel status parity bit mgu609 fig.13 sub-frame format in non-pcm mode.
2002 nov 22 22 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352ts 11.3.1 f ormat of the bitstream the non-pcm data is transmitted in data bursts, consisting of four 16-bit words (called pa, pb, pc and pd) followed by the so called burst-payload. the definition of the burst preambles is given in table 15. table 15 burst preamble words 11.3.2 b urst information the burst information given in preamble pc, meaning the information contained in the data stream, is defined according to iec 60958 as given in table 16. table 16 fields of burst information in preamble pc preamble word length of the field contents value pa 16 bits sync word 1 f872 (hex) pb 16 bits sync word 2 4e1f (hex) pc 16 bits burst information see table 16 pd 16 bits length code number of bits bits of pc value contents reference point r repetition time of data burst in iec 60958 frames 0 to 4 0 null data - none 1 ac-3 data r_ac-3 1536 2 reserved -- 3 pause bit 0 of pa refer to iec 60958 4 mpeg-1 layer 1 data bit 0 of pa 384 5 mpeg-1 layer 1, 2 or 3 data or mpeg-2 without extension bit 0 of pa 1152 6 mpeg-2 with extension bit 0 of pa 1152 7 reserved -- 8 mpeg-2, layer 1 low sampling rate bit 0 of pa 768 9 mpeg-2, layer 2 or 3 low sampling rate bit 0 of pa 2304 10 reserved -- 11 to 13 reserved (dts) - refer to iec 61937 14 to 31 reserved -- 5 to 6 0 reserved -- 7 0 error ?ag indicating a valid burst-payload -- 1 error ?ag indicating an invalid burst-payload -- 8to12 - data type dependant information -- 13 to 15 0 bitstream number --
2002 nov 22 23 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352ts 11.3.3 m inimum burst spacing in order to be able to detect the start of a data burst, it is prescribed to have a data-burst which does not exceed 4096 frames. after 4096 frames there must be a synchronization sequence containing 2 frames of complete zero data (being 4 times 16 bits) followed by the preamble burst pa and pb. in this way a comparison with a sync code of 96 bits can detect the start of a new burst-payload including the pc and pd preambles containing additional stream information. 11.4 timing characteristics 11.4.1 f requency requirements the spdif specification iec 60958 supports three levels of clock accuracy, being: level i, high accuracy: tolerance of transmitting sampling frequency shall be within 50 10 - 6 level ii, normal accuracy: all receivers should receive a signal of 1000 10 - 6 of nominal sampling frequency level iii, variable pitch shifted clock mode: a deviation of 12.5% of the nominal sampling frequency is possible. 11.4.2 r ise and fall times rise and fall times (see fig.14) are defined as: rise time = fall time = rise and fall times should be in the range: 0% to 20% when the data bit is a logic 1 0% to 10% when the data bits are two succeeding logic zeros. 11.4.3 d uty cycle the duty cycle (see fig.14) is defined as: duty cycle = the duty cycle should be in the range: 40% to 60% when the data bit is a logic 1 45% to 55% when the data bits are two succeeding logic zeros. t r t l t h + () -------------------- 100% t f t l t h + () -------------------- 100% t h t l t h + () -------------------- 100% handbook, halfpage 90% t h 50% 10% mgu612 t r t f t l fig.14 rise and fall times.
2002 nov 22 24 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352ts 12 register mapping table 17 register map of control settings (write) table 18 register map of status bits (read-out) register address function system settings 01h spdif mute setting 03h power-down settings interpolator 10h volume control left and right 12h sound feature mode, treble and bass boost 13h mute 14h polarity spdif input settings 30h spdif input settings software reset 7fh restore l3-bus default values register address function interpolator 18h interpolator status spdif input 59h spdif status 5ah channel status bits left [15:0] 5bh channel status bits left [31:16] 5ch channel status bits left [39:32] 5dh channel status bits right [15:0] 5eh channel status bits right [31:16] 5fh channel status bits right [39:32] fpll 68h fpll status
2002 nov 22 25 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352ts 12.1 spdif mute setting (write) table 19 register address 01h table 20 description of register bits bit 15 14 13 12 11 10 9 8 symbol ------- mutebp default ------- 0 bit 76543210 symbol -------- default ----- 000 bit symbol description 15 to 9 - reserved 8 mutebp mute bypass setting. a 1-bit value to disable the mute bypass setting. when this mute bypass setting is enabled, then even in out-of-lock situations or non-pcm data detected, the output data will not be suppressed. if this bit is logic 0, then the output will be muted in out-of-lock situations. if this bit is logic 1, then the output will not be muted in out-of-lock situations. default value 0. 7to3 - reserved 2to0 - when writing new settings via the l3-bus or i 2 c-bus interface, these bits should always remain at logic 0 (default value) to guarantee correct operation.
2002 nov 22 26 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352ts 12.2 power-down settings (write) table 21 register address 03h table 22 description of register bits bit 15 14 13 12 11 10 9 8 symbol -------- default -------- bit 76543210 symbol --- pon_ spdifin -- en_int pondac default --- 10011 bit symbol description 15 to 5 - reserved 4 pon_spdifin power control spdif input. a 1-bit value to enable or disable the power of the iec 60958 bit slicer. if this bit is logic 0, then the power is off. if this bit is logic 1, then the power is on. default value 1. 3to2 - when writing new settings via the l3-bus or i 2 c-bus interface, these bits should always remain at logic 0 (default value) to guarantee correct operation. 1 en_int interpolator clock control. a 1-bit value to control the interpolator clock. if this bit is logic 0, then the interpolator clock is disabled. if this bit is logic 1, then the interpolator clock is enabled. default value 1. 0 pondac power control dac. a 1-bit value to switch the dac into power-on or power-down mode. if this bit is logic 0, then the dac is in power-down mode. if this bit is logic 1, then the dac is in power-on mode. default value 1.
2002 nov 22 27 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352ts 12.3 volume control left and right (write) table 23 register address 10h table 24 description of register bits table 25 volume settings left and right channel bit 15 14 13 12 11 10 9 8 symbol vcl_7 vcl_6 vcl_5 vcl_4 vcl_3 vcl_2 vcl_1 vcl_0 default 00000000 bit 76543210 symbol vcr_7 vcr_6 vcr_5 vcr_4 vcr_3 vcr_2 vcr_1 vcr_0 default 00000000 bit symbol description 15 to 8 vcl_[7:0] volume setting left channel. a 8-bit value to program the left channel volume attenuation. the range is 0 to - 50 db in steps of 0.25 db, to - 60 db in steps of 1 db, - 66 db and - db. default value 0000 0000; see table 25. 7 to 0 vcr_[7:0] volume setting right channel. a 8-bit value to program the right channel volume attenuation. the range is 0 to - 50 db in steps of 0.25 db, to - 60 db in steps of 1 db, - 66 db and - db. default value 0000 0000; see table 25. vcl_7 vcl_6 vcl_5 vcl_4 vcl_3 vcl_2 vcl_1 vcl_0 volume (db) vcr_7 vcr_6 vcr_5 vcr_4 vcr_3 vcr_2 vcr_1 vcr_0 000000000 (default) 00000001 - 0.25 00000010 - 0.5 ::::::::: 11000111 - 49.75 11001000 - 50 11001100 - 51 11010000 - 52 ::::::::: 11110000 - 60 11110100 - 66 11111000 - 11111100 - ::::::::: 11111111 -
2002 nov 22 28 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352ts 12.4 sound feature mode, treble and bass boost settings (write) table 26 register address 12h table 27 description of register bits table 28 sound feature mode table 29 treble settings bit 15 14 13 12 11 10 9 8 symbol m1 m0 tr1 tr0 bb3 bb2 bb1 bb0 default 0 0 0 0 0 0 0 0 bit76543210 symbol -------- default -------- bit symbol description 15 to 14 m[1:0] sound feature mode. a 2-bit value to program the sound processing filter sets (modes) of bass boost and treble. default value 00; see table 28. 13 to 12 tr[1:0] treble settings. a 2-bit value to program the treble setting. the set is selected by the mode bits. default value 00; see table 29. 11 to 8 bb[3:0] bass boost settings. a 4-bit value to program the bass boost settings. the set is selected by the mode bits. default value 0000; see table 30. 7to0 - reserved m1 m0 mode selection 0 0 ?at set (default) 0 1 minimum set 10 1 1 maximum set tr1 tr0 flat set (db) minimum set (db) maximum set (db) 00000 01022 10044 11066
2002 nov 22 29 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352ts table 30 bass boost settings bb3 bb2 bb1 bb0 flat set (db) minimum set (db) maximum set (db) 0000 0 0 0 0001 0 2 2 0010 0 4 4 0011 0 6 6 0100 0 8 8 0101 0 10 10 0110 0 12 12 0111 0 14 14 1000 0 16 16 1001 0 18 18 1010 0 18 20 1011 0 18 22 1100 0 18 24 1101 0 18 24 1110 0 18 24 1111 0 18 24
2002 nov 22 30 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352ts 12.5 mute (write) table 31 register address 13h table 32 description of register bits bit 15 14 13 12 11 10 9 8 symbol qmute mt gs ----- default 0 1 0 -- 000 bit76543210 symbol -------- default -------- bit symbol description 15 qmute quick mute function. a 1-bit value to set the quick mute mode. if this bit is logic 0, then the soft mute mode is selected. if this bit is logic 1, then the quick mute mode is selected. default value 0. 14 mt mute. a 1-bit value to set the mute function. if this bit is logic 0, then the audio output is not muted (unless pin mute is logic 1). if this bit is logic 1, then the audio output is muted. default value 1. 13 gs gain select. a 1-bit value to set the gain of the interpolator path. if this bit is logic 0, then the gain is 0 db. if this bit is logic 1, then the gain is 6 db. default value 0. 12 to 11 - reserved 10 to 8 - when writing new settings via the l3-bus or i 2 c-bus interface, these bits should always remain at logic 0 (default value) to guarantee correct operation. 7to0 - reserved
2002 nov 22 31 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352ts 12.6 polarity (write) table 33 register address 14h table 34 description of register bits bit 15 14 13 12 11 10 9 8 symbol da_pol_ inv ------- default 0 1 ---- 10 bit76543210 symbol -------- default 0 ------- bit symbol description 15 da_pol_inv dac polarity control. a 1-bit value to control the signal polarity of the dac output signal. if this bit is logic 0, then the dac output is not inverted. if this bit is logic 1, then the dac output is inverted. default value 0. 14 - when writing new settings via the l3-bus or i 2 c-bus interface, this bit should always remain at logic 1 (default value) to guarantee correct operation. 13 to 10 - reserved 9 - when writing new settings via the l3-bus or i 2 c-bus interface, this bit should always remain at logic 1 (default value) to guarantee correct operation. 8to7 - when writing new settings via the l3-bus or i 2 c-bus interface, these bits should always remain at logic 0 (default value) to guarantee correct operation. 6to0 - reserved
2002 nov 22 32 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352ts 12.7 spdif input settings (write) table 35 register address 30h table 36 description of register bits bit 15 14 13 12 11 10 9 8 symbol -------- default -------- bit76543210 symbol ---- combine_ pcm burst_ det_en -- default ---- 1100 bit symbol description 15 to 4 - reserved 3 combine_pcm combine pcm detection to lock indicator. a 1-bit value to combine the pcm detection status to the lock indicator. if this bit is logic 0, then the lock indicator does not contain pcm detection status. if this bit is logic 1, then the pcm detection status is combined with the lock indicator. default value 1. 2 burst_ det_en burst preamble settings. a 1-bit value to enable auto mute when burst preambles are detected. if this bit is logic 0, then there is no muting. if this bit is logic 1, then there is muting when preambles are detected. default value 1. 1to0 - when writing new settings via the l3-bus or i 2 c-bus interface, these bits should always remain at logic 0 (default value) to guarantee correct operation.
2002 nov 22 33 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352ts 12.8 interpolator status (read-out) table 37 register address 18h table 38 description of register bits bit 15 14 13 12 11 10 9 8 symbol -------- bit76543210 symbol ----- mute_ s tat e -- bit symbol description 15 to 3 - reserved 2 mute_state mute status bit. a 1-bit value to indicate the status of the mute function. if this bit is logic 0, then the audio output is not muted. if this bit is logic 1, then the mute sequence has been completed and the audio output is muted. 1to0 - reserved
2002 nov 22 34 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352ts 12.9 spdif status (read-out) table 39 register address 59h table 40 description of register bits bit 15 14 13 12 11 10 9 8 symbol -------- bit76543210 symbol ----- burst_ det b_err spdifin_ lock bit symbol description 15 to 3 - reserved 2 burst_det burst preamble detection. a 1-bit value to signal whether burst preamble words are detected in the spdif stream or not. if this bit is logic 0, then no preamble words are detected. if this bit is logic 1, then burst-payload is detected. 1 b_err bit error detection. a 1-bit value to signal whether there are bit errors detected in the spdif stream or not. if this bit is logic 0, then no errors are detected. if this bit is logic 1, then bi-phase errors are detected. 0 spdifin_lock spdif lock indicator. a 1-bit value to signal whether the spdif decoder block is in lock or not. if this bit is logic 0, then the decoder block is out-of-lock. if this bit is logic 1, then the decoder block is in lock.
2002 nov 22 35 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352ts 12.10 channel status (read-out) 12.10.1 c hannel status bits left [15:0] table 41 register address 5ah 12.10.2 c hannel status bits left [31:16] table 42 register address 5bh 12.10.3 c hannel status bits left [39:32] table 43 register address 5ch 12.10.4 c hannel status bits right [15:0] table 44 register address 5dh bit 15 14 13 12 11 10 9 8 symbol spdi_ bit15 spdi_ bit14 spdi_ bit13 spdi_ bit12 spdi_ bit11 spdi_ bit10 spdi_ bit9 spdi_ bit8 bit76543210 symbol spdi_ bit7 spdi_ bit6 spdi_ bit5 spdi_ bit4 spdi_ bit3 spdi_ bit2 spdi_ bit1 spdi_ bit0 bit 15 14 13 12 11 10 9 8 symbol spdi_ bit31 spdi_ bit30 spdi_ bit29 spdi_ bit28 spdi_ bit27 spdi_ bit26 spdi_ bit25 spdi_ bit24 bit76543210 symbol spdi_ bit23 spdi_ bit22 spdi_ bit21 spdi_ bit20 spdi_ bit19 spdi_ bit18 spdi_ bit17 spdi_ bit16 bit 15 14 13 12 11 10 9 8 symbol -------- bit76543210 symbol spdi_ bit39 spdi_ bit38 spdi_ bit37 spdi_ bit36 spdi_ bit35 spdi_ bit34 spdi_ bit33 spdi_ bit32 bit 15 14 13 12 11 10 9 8 symbol spdi_ bit15 spdi_ bit14 spdi_ bit13 spdi_ bit12 spdi_ bit11 spdi_ bit10 spdi_ bit9 spdi_ bit8 bit76543210 symbol spdi_ bit7 spdi_ bit6 spdi_ bit5 spdi_ bit4 spdi_ bit3 spdi_ bit2 spdi_ bit1 spdi_ bit0
2002 nov 22 36 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352ts 12.10.5 c hannel status bits right [31:16] table 45 register address 5eh 12.10.6 c hannel status bits right [39:32] table 46 register address 5fh table 47 description of register bits (two times 40 bits indicating the left and right channel status) bit 15 14 13 12 11 10 9 8 symbol spdi_ bit31 spdi_ bit30 spdi_ bit29 spdi_ bit28 spdi_ bit27 spdi_ bit26 spdi_ bit25 spdi_ bit24 bit76543210 symbol spdi_ bit23 spdi_ bit22 spdi_ bit21 spdi_ bit20 spdi_ bit19 spdi_ bit18 spdi_ bit17 spdi_ bit16 bit 15 14 13 12 11 10 9 8 symbol -------- bit76543210 symbol spdi_ bit39 spdi_ bit38 spdi_ bit37 spdi_ bit36 spdi_ bit35 spdi_ bit34 spdi_ bit33 spdi_ bit32 bit symbol description 39 to 36 - reserved but unde?ned at present 35 to 33 spdi_bit[35:33] word length. a 3-bit value indicating the word length; see table 48. 32 spdi_bit[32] audio sample word length. a 1-bit value to signal the maximum audio sample word length. if bit 32 is logic 0, then the maximum length is 20 bits. if bit 32 is logic 1, then the maximum length is 24 bits. 31 to 30 spdi_bit[31:30] reserved 29 to 28 spdi_bit[29:28] clock accuracy. a 2-bit value indicating the clock accuracy; see table 49. 27 to 24 spdi_bit[27:24] sample frequency. a 4-bit value indicating the sampling frequency; see table 50. 23 to 20 spdi_bit[23:20] channel number. a 4-bit value indicating the channel number; see table 51. 19 to 16 spdi_bit[19:16] source number. a 4-bit value indicating the source number; see table 52. 15 to 8 spdi_bit[15:8] general information. a 8-bit value indicating general information; see table 53. 7 to 6 spdi_bit[7:6] mode. a 2-bit value indicating mode 0; see table 54. 5 to 3 spdi_bit[5:3] audio sampling. a 3-bit value indicating the type of audio sampling; see table 55. 2 spdi_bit2 software copyright. a 1-bit value indicating software for which copyright is asserted or not. if this bit is logic 0, then copyright is asserted. if this bit is logic 1, then no copyright is asserted. 1 spdi_bit1 audio sample word. a 1-bit value indicating the type of audio sample word. if this bit is logic 0, then the audio sample word represents linear pcm samples. if this bit is logic 1, then the audio sample word is used for other purposes. 0 spdi_bit0 channel status. a 1-bit value indicating the consumer use of the status block. this bit is logic 0.
2002 nov 22 37 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352ts table 48 word length table 49 clock accuracy table 50 sampling frequency table 51 channel number spdi_bit35 spdi_bit34 spdi_bit33 word length spdi_bit32 = 0 spdi_bit32 = 1 0 0 0 word length not indicated (default) word length not indicated (default) 0 0 1 16 bits 20 bits 0 1 0 18 bits 22 bits 0 1 1 reserved reserved 1 0 0 19 bits 23 bits 1 0 1 20 bits 24 bits 1 1 0 17 bits 21 bits 1 1 1 reserved reserved spdi_bit29 spdi_bit28 clock accuracy 0 0 level ii 01leveli 1 0 level iii 1 1 reserved spdi_bit27 spdi_bit26 spdi_bit25 spdi_bit24 sampling frequency 0000 44.1 khz 000148khz 001032khz :::: other states reserved 1111 spdi_bit23 spdi_bit22 spdi_bit21 spdi_bit20 channel number 0000 dont care 0001a (left for stereo transmission) 0010b(r ight for stereo transmission) 0011c 0100d 0101e 0110f 0111g 1000h 1001i 1010j 1011k
2002 nov 22 38 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352ts table 52 source number 1100l 1101m 1110n 1111o spdi_bit19 spdi_bit18 spdi_bit17 spdi_bit16 source number 0000 dont care 00011 00102 00113 01004 01015 01106 01117 10008 10019 101010 101111 110012 110113 111014 111115 spdi_bit23 spdi_bit22 spdi_bit21 spdi_bit20 channel number
2002 nov 22 39 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352ts table 53 general information table 54 mode table 55 audio sampling spdi_bit[15:8] function 000 00000 general 100 xxxxl laser optical products 010 xxxxl digital-to-digital converters and signal processing products 110 xxxxl magnetic tape or disc based products 001 xxxxl broadcast reception of digitally encoded audio signals with video signals 011 1xxxl broadcast reception of digitally encoded audio signals without video signals 101 xxxxl musical instruments, microphones and other sources without copyright information 011 00xxl analog-to-digital converters for analog signals without copyright information 011 01xxl analog-to-digital converters for analog signals which include copyright information in the form of cp- and l-bit status 000 1xxxl solid state memory based products 000 0001l experimental products not for commercial sale 111 xxxxl reserved 000 0xxxl reserved, except 000 0000 and 000 0001l spdi_bit7 spdi_bit6 mode 0 0 mode 0 0 1 reserved 10 11 spdi_bit5 spdi_bit4 spdi_bit3 audio sample spdi_bit1 = 0 spdi_bit1 = 1 0 0 0 2 audio samples without pre-emphasis default state for applications other than linear pcm 0 0 1 2 audio samples with 50/15 m s pre-emphasis other states reserved 0 1 0 reserved (2 audio samples with pre-emphasis) 0 1 1 reserved (2 audio samples with pre-emphasis) : : : other states reserved 111
2002 nov 22 40 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352ts 12.11 fpll status (read-out) table 56 register address 68h table 57 description of register bits table 58 lock status indicators of the fpll bit 15 14 13 12 11 10 9 8 symbol ------- fpll_ lock bit76543210 symbol --- vco_ timeout ---- bit symbol description 15 to 9 - reserved 8 fpll_lock fpll lock. a 1-bit value that indicates the fpll status together with bit 4; see table 58. 7to5 - reserved 4 vco_timeout vco time-out. a 1-bit value that indicates the fpll status together with bit 8; see table 58. 3to0 - reserved fpll_lock vco_timeout function 0 0 fpll out-of-lock 0 1 fpll time-out 1 0 fpll in lock 1 1 fpll time-out
2002 nov 22 41 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352ts 13 limiting values in accordance with the absolute maximum rating system (iec 60134). notes 1. all v dd and v ss connections must be made to the same power supply. 2. jedec class 2 compliant. 3. jedec class b compliant. 4. dac operation after short-circuiting cannot be warranted. 14 thermal characteristics 15 characteristics v ddd =v dda = 3.0 v; iec 60958 input with f s = 48.0 khz; t amb =25 c; r l =5k w ; all voltages measured with respect to ground; unless otherwise speci?ed. symbol parameter conditions min. max. unit v dd supply voltage note 1 2.7 5.0 v t stg storage temperature - 65 +125 c t amb ambient temperature - 40 +85 c v esd electrostatic discharge voltage human body model (hbm); note 2 - 2000 +2000 v machine model (mm); note 3 - 200 +200 v i lu(prot) latch-up protection current t amb = 125 c; v dd = 3.6 v - 200 ma i sc(dac) short-circuit current of dac t amb =0 c; v dd = 3 v; note 4 output short-circuited to v ssa(dac) - 20 ma output short-circuited to v dda(dac) - 100 ma symbol parameter conditions value unit r th(j-a) thermal resistance from junction to ambient in free air 110 k/w symbol parameter conditions min. typ. max. unit supplies; note 1 v dda analog supply voltage 2.7 3.0 3.6 v v dda(dac) analog supply voltage for dac 2.7 3.0 3.6 v v dda(pll) analog supply voltage for pll 2.7 3.0 3.6 v v ddd digital supply voltage 2.7 3.0 3.6 v v ddd(c) digital supply voltage for core 2.7 3.0 3.6 v i dda(dac) analog supply current of dac power-on - 3.3 - ma power-down; clock off - 35 -m a i dda(pll) analog supply current of pll - 0.3 - ma i ddd(c) digital supply current of core - 9 - ma i ddd digital supply current - 0.3 - ma p power dissipation dac in playback mode - 38 - mw dac in power-down mode - tbf - mw
2002 nov 22 42 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352ts notes 1. all supply pins v dd and v ss must be connected to the same external power supply unit. 2. when the dac must drive a higher capacitive load (above 50 pf), a series resistor of 100 w must be used to prevent oscillations in the output stage of the operational amplifier. 3. the output voltage of the dac is proportional to the dac power supply voltage. digital inputs v ih high-level input voltage 0.8v ddd - v ddd + 0.5 v v il low-level input voltage - 0.5 - +0.2v ddd v ? i li ? input leakage current -- 10 m a c i input capacitance -- 10 pf r pu(int) internal pull-up resistance 16 33 78 k w r pd(int) internal pull-down resistance 16 33 78 k w digital outputs v oh high-level output voltage i oh = - 2 ma 0.85v ddd -- v v ol low-level output voltage i ol =2ma -- 0.4 v i o(max) maximum output current - 3 - ma digital-to-analog converter; note 2 v o(rms) output voltage (rms value) f i = 1.0 khz tone at 0 dbfs; note 3 850 900 950 mv d v o unbalance of output voltages f i = 1.0 khz tone - 0.1 0.4 db v ref reference voltage measured with respect to v ssa 0.45v dda 0.50v dda 0.55v dda v (thd+n)/s total harmonic distortion-plus-noise to signal ratio f i = 1.0 khz tone at 0 dbfs -- 82 - 77 db at - 40 dbfs; a-weighted -- 60 - 52 db s/n signal-to-noise ratio f i = 1.0 khz tone; code = 0; a-weighted 95 100 - db a cs channel separation f i = 1.0 khz tone - 110 - db spdif input v i(p-p) ac input voltage (peak-to-peak value) 0.2 0.5 3.3 v r i input resistance - 6 - k w v hys hysteresis voltage - 40 - mv symbol parameter conditions min. typ. max. unit
2002 nov 22 43 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352ts 16 timing characteristics v ddd =v dda = 2.4 to 3.6 v; t amb = - 40 to +85 c; r l =5k w ; all voltages measured with respect to ground; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit device reset t rst reset active time - 250 -m s pll lock time t lock time-to-lock f s = 32.0 khz - 85.0 - ms f s = 44.1 khz - 63.0 - ms f s = 48.0 khz - 60.0 - ms l3-bus microcontroller interface; see figs 15 and 16 t cy(clk)(l3) l3clock cycle time 500 -- ns t clk(l3)h l3clock high time 250 -- ns t clk(l3)l l3clock low time 250 -- ns t su(l3)a l3mode set-up time in address mode 190 -- ns t h(l3)a l3mode hold time in address mode 190 -- ns t su(l3)d l3mode set-up time in data transfer mode 190 -- ns t h(l3)d l3mode hold time in data transfer mode 190 -- ns t (stp)(l3) l3mode stop time in data transfer mode 190 -- ns t su(l3)da l3data set-up time in address and data transfer mode 190 -- ns t h(l3)da l3data hold time in address and data transfer mode 30 -- ns t d(l3)r l3data delay time in data transfer mode 0 - 50 ns t dis(l3)r l3data disable time for read data 0 - 50 ns i 2 c-bus microcontroller interface; see fig 17 f scl scl clock frequency 0 - 400 khz t low scl low time 1.3 --m s t high scl high time 0.6 --m s t r rise time sda and scl note 1 20 + 0.1c b - 300 ns t f fall time sda and scl note 1 20 + 0.1c b - 300 ns t hd;sta hold time start condition 0.6 --m s t su;sta set-up time start condition 0.6 --m s t su;sto set-up time stop condition 0.6 --m s t buf bus free time between a stop and start condition 1.3 --m s
2002 nov 22 44 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352ts note 1. c b is the total capacity of one bus line. t su;dat data set-up time 100 -- ns t hd;dat data hold time 0 --m s t sp pulse width of spikes to be suppressed by the input ?lter 0 - 50 ns c b capacitive load for each bus line - 400 pf symbol parameter conditions min. typ. max. unit handbook, full pagewidth t h(l3)a t h(l3)da t su(l3)da t cy(clk)(l3) bit 0 l3mode l3clock l3data bit 7 mgl723 t clk(l3)h t clk(l3)l t su(l3)a t su(l3)a t h(l3)a fig.15 timing for address mode.
2002 nov 22 45 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352ts handbook, full pagewidth t stp(l3) t su(l3)d t h(l3)da t su(l3)da t h(l3)d t cy(clk)l3 bit 0 l3mode l3clock l3data read l3data write bit 7 mbl566 t clk(l3)h t clk(l3)l t d(l3)r t dis(l3)r fig.16 timing for data transfer mode. handbook, full pagewidth msc610 s sr t su;sto t su;sta t hd;sta t high t low t su;dat t hd;dat t f sda scl p s t buf t r t f t r t sp t hd;sta fig.17 timing of the i 2 c-bus transfer.
2002 nov 22 46 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352ts this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 17 application information handbook, full pagewidth mgu657 uda1352ts 17 4 voutr 28 25 right_out hlmp-1385 (2x) s5 v ddd 0 1 2 3 s6 s4 v ddd 1 0 1 1 s1 v ddd l3-bus or i 2 c-bus static 2 3 1 2 3 v ddd i 2 c-bus l3-bus 1 2 3 s7 v ddd rst norm 1 2 3 16 r3 1 k w d1 1 r9 1 k w d2 pcmdet n.c. 27 22 n.c. n.c. 21 5 lock da0 seliic 26 selstatic s2 v ddd no mute mute 2 3 1 11 mute da1 c18 47 m f (16 v) x3 r8 10 k w r7 100 w 15 19 voutl vref left_out c17 47 m f (16 v) x2 r6 10 k w r5 100 w reset 18 24 23 test2 c15 100 nf (50 v) c14 10 m f (16 v) c20 100 m f (16 v) c21 100 m f (16 v) l3 blm31a601s c13 100 nf (50 v) c12 100 m f (16 v) v dda v dda(dac) 14 v ssa(dac) 20 v ssd 7 v ssd(c) v ddd(c) 12 v ddd v dda v ddd 3 l2 blm31a601s c5 100 nf (50 v) c4 100 m f (16 v) v ddd 6 l1 blm31a601s c3 100 nf (50 v) c2 100 m f (16 v) v dda c6 180 pf (50 v) c7 10 nf (50 v) r10 75 w x1 spdif 13 v dda(pll) v ssa(pll) c11 100 nf (50 v) c10 100 m f (16 v) v ddd + 3 v gnd r4 1 w l3clock 9 l3mode 10 l3data 8 fig.18 application diagram.
2002 nov 22 47 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352ts 18 package outline unit a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm 0.21 0.05 1.80 1.65 0.38 0.25 0.20 0.09 10.4 10.0 5.4 5.2 0.65 1.25 7.9 7.6 0.9 0.7 1.1 0.7 8 0 o o 0.13 0.1 0.2 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.20 mm maximum per side are not included. 1.03 0.63 sot341-1 mo-150 95-02-04 99-12-27 x w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 114 28 15 0.25 y pin 1 index 0 2.5 5 mm scale ssop28: plastic shrink small outline package; 28 leads; body width 5.3 mm sot341-1 a max. 2.0
2002 nov 22 48 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352ts 19 soldering 19.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for fine pitch smds. in these situations reflow soldering is recommended. 19.2 re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 220 c for thick/large packages, and below 235 c for small/thin packages. 19.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 19.4 manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
2002 nov 22 49 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352ts 19.5 suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales office. 2. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 3. these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 5. wave soldering is suitable for lqfp, tqfp and qfp packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. wave soldering is suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. package (1) soldering method wave reflow (2) bga, lbga, lfbga, sqfp, tfbga, vfbga not suitable suitable hbcc, hbga, hlqfp, hsqfp, hsop, htqfp, htssop, hvqfn, hvson, sms not suitable (3) suitable plcc (4) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (4)(5) suitable ssop, tssop, vso not recommended (6) suitable
2002 nov 22 50 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352ts 20 data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. 3. for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level data sheet status (1) product status (2)(3) definition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn). 21 definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 22 disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2002 nov 22 51 philips semiconductors preliminary speci?cation 48 khz iec 60958 audio dac uda1352ts 23 purchase of philips i 2 c components purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
? koninklijke philips electronics n.v. 2002 sca74 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors C a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales of?ces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . printed in the netherlands 753503/02/pp 52 date of release: 2002 nov 22 document order number: 9397 750 10469

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